FreeCAD: master 0f33a09c

Author Committer Branch Timestamp Parent
marioalexis marioalexis master 2021-01-22 04:16:16 master f30cbf6b
Changeset Draft: Prevent Draft_Wire from setting a single-edge wire as closed
mod - src/Mod/Draft/draftguitools/gui_lines.py Diff File